1. Field of the Invention
The present invention relates generally to parallel analog-to-digital converter systems.
2. Description of the Related Art
Extremely high conversion rates may be obtained by operating a plurality of analog-to-digital converters in a parallel converter system. For example, analog input signals can be converted to a corresponding digital code at speeds up to a system rate fS by paralleling M converters that each process samples of the analog input signal at a maximum converter rate fS/M. Stated differently, M converters that are each limited to a maximum converter rate fcnvrtr can be combined to realize a system rate of Mfcnvrtr.
However, when parallel converters are operated in a fixed sequence (e.g., A, B, C, A - - - ), it has been found that parameter mismatches between the converters (e.g., gain, offset and timing mismatches) generate conversion errors which exhibit repetitive patterns that generate spurious signals in the spectrum of the output digital code.
It has been found that the spurious signals can be reduced by altering the fixed sequence in which the parallel converters are operated. In a parallel system in which the converters are pipelined converters, for example, the residue of a converter stage of one converter has been directed to a subsequent stage in a randomly-selected one of the other converters. This structure has been found to reduce the spurious signals but is quite complex and does not address parameter mismatch in the system""s samplers.
It has also been found that the spurious signals can be reduced by adding at least one additional converter to a parallel system so that at least one converter is idling at any given moment. A random choice is made between the idling converter and a converter that has just completed its conversion and the chosen converter processes a successive sample. This system does not insure that all converters are constantly processing signals and, accordingly, a converter may remain idle for some time which leads to conversion errors in converters that include switched-capacitor structures.
The present invention is directed to parallel converters and methods that reduce spurious signals in systems that provide samples of an analog input signal in successive system periods.
In a system embodiment of the invention, a plurality of analog-to-digital converters are partitioned into at least two converter groups which are assigned different respective group converter periods that are multiples of the system periods. With converters in each of the converter groups, respective samples are processed over that group""s respective group converter period and the group converter periods of all converters are temporally shifted to process each of the samples with at least one of the converters.
In another embodiment, the reduced spurious lines are converted into the system""s noise level by detecting instances when available converters that belong to different converter groups are available to process an upcoming one of the samples and, in at least a chosen one of the instances, exchanging the available converters between their different converter groups to thereby alter which processes the upcoming sample and which processes a subsequent sample. All converters continue to process respective samples.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.